x86 sets its aim on super low power applications
For those wondering, about whether Intel Corp.'s (INTC) new Quark chip might use an an instruction set from ARM Holdings plc (LON:ARM) or MIPS (a recent acquisition of Imagination Technologies Group Plc (LON:IMG)), wonder no longer.
I spoke with several Intel executives and PR people and together they dug up some more information on the processor for me. It's a 32-bit design, and features a standard Pentium compatible (i.e. x86) instruction set.
EETimes corroborates this information, reportedly hearing it from Intel's CEO Brian Krzanich himself. That report also reveals that the chip shown at the morning press keynote was a 32 nm design, a die shrink up from Intel's current 22 nm node.
Some have questioned how Intel could get a 32-bit Atom processor scaled down enough to fit on 1/5th the die size and 1/10th the. I don't really see how it's that unfathomable.
Let's look at Intel's Atom die, circa April 2008 (Silverthorne, 45 nm):
A die shot of Intel Atom Silverthorne [Image Source: Intel Confidential via AnandTech]
Remember many small microcontrollers have no cache.
Take away that healthy chunk of L2 cache and perhaps the L1 cache associated with the memory execution cluster (MEC) and the front-end cluster (FEC), as well and you eliminate perhaps half the die. Eliminate one of the two I/O buses and you get even closer. Cut out an ALU from the floating-point cluster (FPC) and integer (arithmetic) processing clusters (IPCs) (Atom chips have at least 2 ALUs per cluster) and you're pretty much there, albeit at the expense of sacrificing multithreading.
But then again, cutting ALUs or I/O may be unnecessary as Intel may be comparing a GPU-less Quark's die-size to a recent Atom, most of which pack GPUs.
The lighter chip should inherently use a great deal less power. Cut the clock down from the 1+ GHz Atoms run at to perhaps 500 or 600 MHz and you're likely at 1/10th power consumption.
For those wondering, about whether Intel Corp.'s (INTC) new Quark chip might use an an instruction set from ARM Holdings plc (LON:ARM) or MIPS (a recent acquisition of Imagination Technologies Group Plc (LON:IMG)), wonder no longer.
I spoke with several Intel executives and PR people and together they dug up some more information on the processor for me. It's a 32-bit design, and features a standard Pentium compatible (i.e. x86) instruction set.
EETimes corroborates this information, reportedly hearing it from Intel's CEO Brian Krzanich himself. That report also reveals that the chip shown at the morning press keynote was a 32 nm design, a die shrink up from Intel's current 22 nm node.
Some have questioned how Intel could get a 32-bit Atom processor scaled down enough to fit on 1/5th the die size and 1/10th the. I don't really see how it's that unfathomable.
Let's look at Intel's Atom die, circa April 2008 (Silverthorne, 45 nm):
A die shot of Intel Atom Silverthorne [Image Source: Intel Confidential via AnandTech]
Remember many small microcontrollers have no cache.
Take away that healthy chunk of L2 cache and perhaps the L1 cache associated with the memory execution cluster (MEC) and the front-end cluster (FEC), as well and you eliminate perhaps half the die. Eliminate one of the two I/O buses and you get even closer. Cut out an ALU from the floating-point cluster (FPC) and integer (arithmetic) processing clusters (IPCs) (Atom chips have at least 2 ALUs per cluster) and you're pretty much there, albeit at the expense of sacrificing multithreading.
But then again, cutting ALUs or I/O may be unnecessary as Intel may be comparing a GPU-less Quark's die-size to a recent Atom, most of which pack GPUs.
The lighter chip should inherently use a great deal less power. Cut the clock down from the 1+ GHz Atoms run at to perhaps 500 or 600 MHz and you're likely at 1/10th power consumption.
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